Control resynthesis for control-dominated asynchronous designs
- 23 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown to generate efficient asynchronous implementations. However for control-dominated designs where the data processing parts play a relatively minor role, we believe the solutions produced by pure syntax directed translation methods may be significantly improved. In this paper we consider the problem of resynthesizing the control parts of the syntax directed translation solutions by means of STG based algorithmic synthesis approaches. This involves a strategy for partitioning between the control and data processing parts, algorithms for reconstructing the STGs from the control partitions, and a strategy for resynthesizing these reconstructed STGs using existing STG-based synthesis approaches. We show with a realistic design experiment that our control resynthesis approach can offer significant improvements over pure syntax directed translation solutions.Keywords
This publication has 22 references indexed in Scilit:
- Synthesis Of Concurrent System Interface Modules With Automatic Protocol Conversion GenerationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Performance-driven Synthesis Of Asynchronous ControllersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- VLSI programming and silicon compilation-a novel approach from Philips researchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Practical asynchronous controller designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of 3D asynchronous state machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Solving the state assignment problem for signal transition graphsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Optimised state assignment for asynchronous circuit synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- Basic gate implementation of speed-independent circuitsPublished by Association for Computing Machinery (ACM) ,1994
- Compiling communicating processes into delay-insensitive VLSI circuitsDistributed Computing, 1986