Stacking Faults in Annealed Silicon Surfaces

Abstract

Mechanical polishing can generate a flowed lattice and minute crevices in silicon surfaces. Dislocations and stacking faults develop during high‐temperature annealing treatments. A systematic investigation of the fault has led to proposed mechanisms for stacking‐fault formation, growth, and annihilation. Fault nucleation appears to occur at pinning centers in the flowed lattice provided by crevices fixed by a thermally grown silicon dioxide film. Such pinning centers increase the probability of dislocations intersecting with one another. The intersection of two dislocations which satisfies the Lomar‐Cottrell conditions will form a stacking fault. The stacking faults which form in the above dynamic system are extrinsic, bound by ⅓ [111] Frank partials. Such faults grow by vacancy emission. Enhanced fault growth is provided by the dynamic recovering lattice. Fault annihilation can occur if the vacancies emitted by the enhanced fault growth are not annihilated. The Si–SiO₂ interface appears to be the dominant vacancy sink during the period of rapid oxide growth.