A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers
- 1 March 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (3), 312-320
- https://doi.org/10.1109/4.557628
Abstract
No abstract availableThis publication has 21 references indexed in Scilit:
- An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 2.5 V 12 b 5 MSample/s pipelined CMOS ADCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CMOS folding ADCs with current-mode interpolationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 10 b, 20 Msample/s, 35 mW pipeline A/D converterIEEE Journal of Solid-State Circuits, 1995
- An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADCIEEE Journal of Solid-State Circuits, 1995
- A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverterIEEE Journal of Solid-State Circuits, 1994
- Efficient circuit configurations for algorithmic analog to digital convertersIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1993
- A 10-b 20-Msample/s analog-to-digital converterIEEE Journal of Solid-State Circuits, 1992
- A pipelined 5-Msample/s 9-bit analog-to-digital converterIEEE Journal of Solid-State Circuits, 1987
- Considerations for high-frequency switched-capacitor ladder filtersIEEE Transactions on Circuits and Systems, 1980