An efficient implementation of Boolean functions as self-timed circuits
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 41 (1), 2-11
- https://doi.org/10.1109/12.123377
Abstract
The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided.Keywords
This publication has 9 references indexed in Scilit:
- A hardware semantics based on temporal intervalsPublished by Springer Science and Business Media LLC ,2005
- An efficient implementation of Boolean functions as self-timed circuitsIEEE Transactions on Computers, 1992
- The Limitations to Delay-Insensitivity in Asynchronous CircuitsPublished by Springer Science and Business Media LLC ,1990
- Recent developments in the design of asynchronous circuitsLecture Notes in Computer Science, 1989
- Compiling communicating processes into delay-insensitive VLSI circuitsDistributed Computing, 1986
- A Temporal Logic for Multilevel Reasoning about HardwareComputer, 1985
- Trace Theory and VLSJ DesignLecture Notes in Computer Science, 1985
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Science and Business Media LLC ,1984
- Temporal Specifications of Self-Timed SystemsPublished by Springer Science and Business Media LLC ,1981