Cascode voltage switch logic: A differential CMOS logic family

1 January 1984

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 16-17
https://doi.org/10.1109/isscc.1984.1156629

Abstract

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

Keywords

SWITCHES
CMOS LOGIC CIRCUITS
VOLTAGE
LOGIC DEVICES
MOS DEVICES
LOGIC DESIGN
LOGIC CIRCUITS
CMOS TECHNOLOGY
DELAY
BOOLEAN FUNCTIONS

This publication has 2 references indexed in Scilit:

Optimization by Simulated Annealing
Science, 1983
High-speed compact circuits with CMOS
IEEE Journal of Solid-State Circuits, 1982

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