A Way to Build Efficient Carry-Skip Adders
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-36 (10), 1144-1152
- https://doi.org/10.1109/tc.1987.1676855
Abstract
In this paper, we present a way to obtain efficient carry-skip adders, built with blocks of different sizes in VLSI technologies. We give some results about two-level carry-skip adders. We reduce our optimization problem to a geometrical problem, solved by means of an algorithm easily implemented on a microcomputer. Then we present an example of the realization of such an adder.Keywords
This publication has 6 references indexed in Scilit:
- Some optimal schemes for ALU implementation in VLSI technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A comparison of ALU structures for VLSI technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A 32-bit execution unit in an advanced NMOS technologyIEEE Journal of Solid-State Circuits, 1982
- Review of high-speed addition techniquesProceedings of the Institution of Electrical Engineers, 1971
- On Determination of Optimal Distributions of Carry Skips in AddersIEEE Transactions on Electronic Computers, 1967
- Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic UnitsIEEE Transactions on Electronic Computers, 1961