A Methodology for Worst-Case Analysis of Integrated Circuits
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 5 (1), 104-113
- https://doi.org/10.1109/tcad.1986.1270181
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- FABRICS II: A Statistically Based IC Fabrication Process SimulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Statistical Simulation of the IC Manufacturing ProcessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982