A Three-Level Space Vector Modulation Scheme for Paralleled Converters to Reduce Circulating Current and Common-Mode Voltage

Abstract

For high-power applications, paralleling converters is a popular approach to increase the power capacity of the system. Circulating current has been a major concern for the implementation of paralleled converters. This paper proposes a three-level space vector modulation (SVM) scheme for a system with two paralleled voltage-source converters (VSCs) with common-mode inductor (CMI) or single-phase inductors. The proposed scheme aims to reduce the zero-sequence circulating current (ZSCC) and the magnitude of common-mode voltage (CMV) of the system simultaneously. The ZSCC patterns with respect to modulation schemes are first analyzed to provide a clear understanding of the generation of ZSCC. Based on the analysis, the proposed three-level modulation scheme is introduced. Furthermore, performance regarding the ZSCC peak value, impact on the common-mode current (CMC), CMI scaling analysis, and switching losses are analyzed and compared with the existing methods. The proposed method has been verified in both simulation and experiment.