A 1-V low-power high-performance 32-bit conditional sum adder

Publisher Website

17 December 2002

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/lpe.1994.573206

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
IEEE Journal of Solid-State Circuits, 1993
Conditional-Sum Addition Logic
IEEE Transactions on Electronic Computers, 1960

Cited by 7 articles