The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-32 (10), 902-910
- https://doi.org/10.1109/tc.1983.1676134
Abstract
This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows.Keywords
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