BiNMOS design constraints for 0.3 < Leff < 0.4 microns

Abstract

BiNMOS gates lose some of their performance advantage over CMOS as Vcc scales down to meet hot electron reliability constraints with shorter Leff. Some BiNMOS applications have reliability concerns with the EB junction is reverse biased. PMOS subthreshold current, noise margin, and capacitive coupling effects also must be considered to maintain a robust BiNMOS design strategy. The NPN size must be carefully optimized relative to MOS transistor sizes, gate configuration, and fanout in order to provide an adequate performance advantage. These concerns are addressed for BiNMOS gates with 0.3 < Leff < 0.4 microns.