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Timing analysis in a logic synthesis environment
Home
Publications
Timing analysis in a logic synthesis environment
Timing analysis in a logic synthesis environment
NW
N. Weiner
N. Weiner
A. Sangiovanni-Vincentelli
A. Sangiovanni-Vincentelli
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1 January 1989
conference paper
Published by
Association for Computing Machinery (ACM)
https://doi.org/10.1145/74382.74498
Abstract
No abstract available
Cited by 9 articles