Abstract
When linear voltage ramps were applied to MOS capacitors, the current‐vs‐voltage (IV) curves indicated a region of quasisaturation of current, i.e., a ledge in the IV characteristic. These ledges could be explained by an electron‐trapping model. Trap cross sections and concentrations were dependent on sample processing and oxide thickness and were in the 10−19 cm2 and 1012 cm−2 ranges, respectively. Comparison of shifts in the IV and CV curves showed that trapped charge to be within about 10 Å of the Si‐SiO2 interface.