Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's
- 1 October 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 15 (10), 386-388
- https://doi.org/10.1109/55.320976
Abstract
To optimize the V/sub th/ of double-gate SOI MOSFET's, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.Keywords
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