A CCITT standard 32 kbps ADPCM LSI codec

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 10, 1425-1428
https://doi.org/10.1109/icassp.1985.1168091

Abstract

An LSI ADPCM codec, which is based on the CCITT standard 32 kbps algorithm, has been developed. The LSI chip has been designed as a software controllable signal processor whose architecture is optimized for the CCITT algorithm. A reconfigurable pipeline multiplier-normalizer-accumulator circuit is effectively utilized for realizing complex ADPCM specifications. The LSI chip, implemented by 2.5 µ CMOS technology, dissipates only 90 milliwatts of power.

Keywords

CODE STANDARDS
LARGE SCALE INTEGRATION
CODECS
SIGNAL PROCESSING ALGORITHMS
CMOS TECHNOLOGY
STANDARDS DEVELOPMENT
SOFTWARE DESIGN
SIGNAL DESIGN
ALGORITHM DESIGN AND ANALYSIS
PROCESS CONTROL

This publication has 1 reference indexed in Scilit:

A single chip signal processor for CCITT standard ADPCM codec
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985

Cited by 2 articles