A Graphical Interpretation of Realization of Symmetric Boolean Functions with Threshold Logic Elements
- 1 February 1965
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers
- Vol. EC-14 (1), 8-18
- https://doi.org/10.1109/pgec.1965.264028
Abstract
A graphical interpretation of the realization of symmetric Boolean functions with threshold logic elements is presented, from which a systematic synthesis method is developed. Theoretically, symmetric functions of any number of variables can be realized. Examples are given to show that, practically, there is no difficulty at all in realizing symmetric Boolean functions of as many as thirty or forty variables. Some theorems related to graphical interpretation and realization are presented, and the lower and upper bounds of the number of threshold logic elements required for the realization of symmetric functions are also derived from the graphical point of view.Keywords
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