Parallel bit-level pipelined VLSI designs for high-speed signal processing

Abstract

This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in designing such fully pipelined architectures. These include clock skew, clock distribution networks, buffering, timing simulation, area overhead due to pipelining, and testing. A total of six bit-level pipelined designs, including a multiplier, an FIR filter block, and a multichannel multiply-accumulate/add chip, have now been fabricated in CMOS technology. These chips have been tested both for functionality and speed. The results of these tests and the applications of these chips are presented and discussed.