An nMOS VLSI process for fabrication of a 32-bit CPU chip
- 1 October 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (5), 542-547
- https://doi.org/10.1109/jssc.1981.1051635
Abstract
An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology utilizes 1.5-/spl mu/m lines and 1.0-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization. The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow. Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology.Keywords
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