High-performance NMOS operational amplifier
- 1 December 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (6), 760-766
- https://doi.org/10.1109/jssc.1978.1052047
Abstract
A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 /spl mu/V; C-message weighted noise -5 dBrnC; and 0.1-percent settling time, 2.5 /spl mu/s.Keywords
This publication has 6 references indexed in Scilit:
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