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Publications
Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
Home
Publications
Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
DT
D. E. Thomas
D. E. Thomas
EL
E. D. Lagnese
E. D. Lagnese
RW
R. A. Walker
R. A. Walker
JN
J. A. Nestor
J. A. Nestor
JR
J. V. Rajan
J. V. Rajan
RB
R. L. Blackburn
R. L. Blackburn
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1 January 1990
book
Published by
Springer Nature
https://doi.org/10.1007/978-1-4613-1519-3
Abstract
No abstract available
Keywords
PHASE
ALGORITHMS
CIRCUIT DESIGN
COMPUTER
COMPUTER-AIDED DESIGN (CAD)
DESIGN PROCESS
DEVELOPMENT
FILTER
INTEGRATED CIRCUIT
LOGIC
MICROPROCESSOR
MODEL
MODELING
Cited by 96 articles