A programmable CMOS dual channel interface processor for telecommunications applications
- 1 December 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (6), 892-899
- https://doi.org/10.1109/jssc.1984.1052242
Abstract
A CMOS analog VLSI chip for telecommunications applications has been designed in which many desirable line card features are programmable through a unique interface from the central switching office. The authors emphasize the circuit innovations of some key analog functions realized on the chip, specifically, the operational amplifier family, the precision bandgap reference circuit, and the line balancing function. The die size of the analog VLSI is approximately 50000 mils/SUP 2/, and the active power dissipation is 80 mW with a 1 mW standby mode.Keywords
This publication has 8 references indexed in Scilit:
- Large swing CMOS power amplifierIEEE Journal of Solid-State Circuits, 1983
- A precision curvature-compensated CMOS bandgap referenceIEEE Journal of Solid-State Circuits, 1983
- An improved frequency compensation technique for CMOS operational amplifiersIEEE Journal of Solid-State Circuits, 1983
- A family of differential NMOS analog circuits for a PCM codec filter chipIEEE Journal of Solid-State Circuits, 1982
- A single-chip CMOS PCM CODEC with filtersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A monolithic NMOS filter and line balance chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- A precision reference voltage sourceIEEE Journal of Solid-State Circuits, 1973
- New developments in IC voltage regulatorsIEEE Journal of Solid-State Circuits, 1971