A four-quadrant NMOS analog multiplier
- 1 December 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (6), 1174-1178
- https://doi.org/10.1109/jssc.1982.1051877
Abstract
A four-quadrant NMOS analog multiplier, which achieves linearity better than 0.3 percent at 75 percent of full-scale swing, a bandwidth of DC to 1.5 MHz, and output noise 77 dB below full scale is described. Active area is 450 mils/SUP 2/.Keywords
This publication has 5 references indexed in Scilit:
- A high-performance monolithic multiplier using active feedbackIEEE Journal of Solid-State Circuits, 1974
- Distortion in bipolar transistor variable-gain amplifiersIEEE Journal of Solid-State Circuits, 1973
- Applications of a monolithic analog multiplierIEEE Journal of Solid-State Circuits, 1968
- A new wide-band amplifier techniqueIEEE Journal of Solid-State Circuits, 1968
- A precise four-quadrant multiplier with subnanosecond responseIEEE Journal of Solid-State Circuits, 1968