An optimizer for hardware synthesis
- 1 October 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 7 (5), 20-36
- https://doi.org/10.1109/54.60604
Abstract
A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.Keywords
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