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Optimization of the PLA Area
Home
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Optimization of the PLA Area
Optimization of the PLA Area
JP
J.F. Paillotin
J.F. Paillotin
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1 January 1981
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/dac.1981.1585388
Abstract
A method to reduce the area of the PLA's is presented. Two steps are considered : the permutation of the minterms (columns) and the compacting of the PLA. The method is illustrated on the NMOS technology.
Keywords
PROGRAMMABLE LOGIC ARRAYS
MOS DEVICES
ALUMINUM
VERY LARGE SCALE INTEGRATION
CIRCUITS
MERGING
DESIGN AUTOMATION
INVERTERS
JOINING PROCESSES
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Open Access
Cited by 11 articles