High-K dielectrics for the gate stack

Abstract

This article gives an overview of recent developments in the search for the next-generation dielectric for the complementary metal-oxide semiconductor gate stack. After introducing the main quantities of interest, the paper concentrates on a figure of merit that connects two main properties of the gate stack, namely, the leakage current and the capacitance. This is done for single layers as well as for bilayers consisting of interfacial $\mathrm{Si}{\mathrm{O}}_x$ and a high-$K$ dielectric. In the case of the bilayers, the impact of the interfacial layer $\mathrm{Si}{\mathrm{O}}_x$ is enormous, reducing the leakage current by an order of magnitude per monolayer. This extreme dependance makes a good correlation between the leakage and the structural parameters nearly impossible. This is illustrated using numerical examples designed to help the reader evaluate the orders of magnitude involved. The origin of the interfacial layer is traced back by means of thermodynamic considerations. As the estimates put forward in the literature do not correspond to the results observed, a detailed review is made, and additional mechanisms are suggested. By using reasonable values for the Gibbs free energy of an interfacial solid silicon oxide phase it is demonstrated how the reaction equilibria shift. Such an interface phase may fundamentally change the stability criteria of oxides on Si. Furthermore, it can also provide a major source of electronic defects that will affect the device performance. Finally, a second figure of merit is introduced that connects the capacitance with a strongly reduced carrier mobility, which might also be related to the same electronic defects.