Evaluation of Passivated Integrated Circuits Using the Scanning Electron Microscope

Abstract

By examining passivated silicon integrated circuits in the scanning electron microscope, the surface contours of p‐n junctions have been mapped, potential drops across integrated resistors have been observed, and physical characteristics of the oxide surface, evaporated leads, and bonded gold wires have been determined. Typical faults discovered by this method of testing include poor registration, improperly masked diffusions, harmful and nonharmful surface scratches, poor evaporated interconnections, and defective passivation oxide layers. Most junctions in a 40 mil square integrated circuit can be delineated with 1μ resolution in approximately 1 min by this technique.