Design of a FASTBUS Programmable Sequencer Module and Memory Module

Abstract

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.

Keywords

FASTBUS
RANDOM ACCESS MEMORY
READ-WRITE MEMORY
PROTOCOLS
MASTER-SLAVE
REGISTERS
COUNTING CIRCUITS
LINEAR ACCELERATORS
CIRCUIT SYNTHESIS
PROTOTYPES

Cited by 3 articles