Automatic Generation and Characterization of CMOS Polycells

Abstract

With increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. An approach to take advantage of these aids is the polycell design approach. However, thus far, manual procedures have been used in creating the interior of polycells. A layout style in which CMOS technology lends itself to automation and design rule updatability has been found and is described here. A program has been implemented which takes as input a symbolic description of polycells and a set of design rules, and outputs a mask description of polycells. This mask description and a command file are then input to a layout characterization and verification software system to automatically generate inputs for a polycell layout system, a circuit simulator, and a timing simulator.