A Self-Aliglned 1-/spl mu/m-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy
- 1 February 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (1), 123-129
- https://doi.org/10.1109/jssc.1985.1052284
Abstract
A six-mask 1-/spl mu/m CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p/sup +/ substrate and a retrograde n-well. Self-aligned TiSi/sub 2/ is formed on n/sup +/ and p/sup +/ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n/sup +/ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is dernonstrated that this CMOS technology is Iatchup free since the holding voltage for Iatchup is higher than 5 V.Keywords
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