An experimental 64-bit decoded Josephson NDRO random access memory
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5), 591-600
- https://doi.org/10.1109/jssc.1978.1051105
Abstract
The design and testing of an experimental fully decoded 64-bit Josephson NDRO (nondestructive readout) RAM chip are described. Tree decoders were used to access the memory cells. The basic memory cell was a ring cell containing a single write gate. The chips were built in a coarse 25 /spl mu/m technology since neither speed nor density were stressed in this study. An access time of 4 ns with full margins and of 2.3 ns with reduced margins were demonstrated. The corresponding full memory cycle times were 5 and 3.5 ns, respectively. Good agreement with computer simulations was obtained throughout.Keywords
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