We use the LER measurement capabilities of the Applied Materials NanoSEM 3D CD-SEM for the determination of LER for different manufacturing steps of the DRAM gate layer for the 90 nm technology node and below (after develop, after hard mask-open and final inspection steps). The system allows the fully automatic measurement of the LER as a 3 sigma value for top as well as bottom LER and yields also information about the spatial frequency along the line edge. We demonstrate precision of LER measurements (3 sigma) of less than 10% of the LER for resist structures as well as for etched structures with random or artificial LER within a range from 4 to 20 nm LER. The results agree with the requirements of the ITRS roadmap for structures down to 70 nm. We show on etched poly wafers containing artificial LER that the identification of discrete frequencies is possible down to LER values of below 5 nm (3 sigma). Based on these result we investigate LER on product wafers and show that the LER of left and right line edge, repsectively, are independent of each other. Additionally, no significant discrete frequencies are detected for all process steps under investigation, although the LER amplitude varies significantly in dependence of process conditions.