A half-micron CMOS technology using ultra-thin silicon on insulator

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01631918,p. 583-586
https://doi.org/10.1109/iedm.1990.237131

Abstract

A 0.5 mu m CMOS technology on ultra-thin film SIMOX SOI (silicon on insulator) material is described. The technology, material quality, and device properties are discussed. The impact of TiSi/sub 2/ salicidation on the NMOS device breakdown, self-heating, and anomalous hot carrier degradation of NMOS devices is discussed in detail. Furthermore, the successful fabrication of a large circuit with 70000 transistors using a 0.5 mu m technology on ultra-thin SOI material is presented.<>

Keywords

CMOS TECHNOLOGY
SILICON ON INSULATOR TECHNOLOGY
MOS DEVICES
SEMICONDUCTOR FILMS
ELECTRIC BREAKDOWN
HOT CARRIERS
DEGRADATION
FABRICATION
CIRCUITS

This publication has 1 reference indexed in Scilit:

Single-transistor latch in SOI MOSFETs
IEEE Electron Device Letters, 1988

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