A virtual self-aligned process for n-channel InP IGFET's (or MISFET's)

1 November 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 2 (11), 299-301
https://doi.org/10.1109/EDL.1981.25441

Abstract

A virtual self-aligned process for fabricating IGFET's (or MISFET's) has been developed. Devices fabricated on semiinsulating InP substrates using this process show: (i) square-law characteristics, (ii) an inverse-relationship between transconductance and gate length, and (iii) high surface channel electron mobilities on the order of 1000 cm2/v.sec.

Keywords

INDIUM PHOSPHIDE
ION IMPLANTATION
RESISTS
INSULATION
ANNEALING
GOLD
ETCHING
TRANSCONDUCTANCE
ELECTRON MOBILITY
MICROWAVE DEVICES

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