SIMULATION OF THERMAL NOISE IN SCALED MOSFETS

Abstract

In this work, hydrodynamic device simulations and a post-processor for the simulation of noise in MOSFETs are applied in order to evaluate the impact of scaling on the thermal noise of transistors representative of technologies with minimum gate length scaled from 0.25 μm down to 0.1 μm. The dependences on bias and technology scaling of the spectral densities of the equivalent drain- and induced gate-noise currents are anayzed in details. The effect of technology scaling on the two-port noise parameters of the intrinsic MOSFET is studied as well. The results of this work confirm that the transistor's noise performance tend to improve as the technology is scaled down, making CMOS a suitable technological option for the implementation of advanced low-power RF systems.