Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
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This publication has 1 reference indexed in Scilit:
- Surface conduction in short-channel MOS devices as a limitation to VLSI scalingIEEE Transactions on Electron Devices, 1982