Gate oxide integrity and minority-carrier lifetime correlated with Si wafer polish damage

Abstract

This study investigated the effects of Si wafer polish damage on the electrical performance and integrated circuits, using metal‐oxide‐semiconductor capacitors as the test structures. These test capacitors were fabricated with 100 or 250 Å oxide layers thermally grown on wafers having varied polish‐damaged surfaces. Field‐dependent and time‐dependent breakdown data were measured and correlated with the surface polish quality as characterized by thermal wave (TW) modulated reflectance measurements. To study the effects of damage remaining in the silicon beneath the Si/SiO₂ interface after the formation of the capacitors, the minority‐carrier lifetime was measured and also correlated with the TW values obtained on the starting (nonprocessed) wafer surfaces. The results of this study established that increased polish damage, indicated by higher TW values, adversely affects thin oxide breakdown integrity and reduces the minority‐carrier lifetime.