Major issues involved in the optimization of trench capacitors for VLSI DRAMs are considered, using the previously described 4Mb DRAM cross-point Trench-Transistor Cell (TTC) as a vehicle. The effects of capacitor plate doping, trench etch angle and depth on the capacitance of the trench capacitor are studied. Pisces-II simulations show that there is adequate electrical isolation between adjacent cells, with a grounded substrate. Any tendencies for intercell leakage are further minimized, by reverse-biasing the substrate at-2.0V. High-resolution TEM and lattice imaging techniques are utilized to study the quality of oxide dielectric in the trench capacitor. In addition, a simple way of enlarging the capacitor area, in order to increase the storage capacitance, is presented.