A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5), 554-561
- https://doi.org/10.1109/JSSC.1983.1051993
Abstract
A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.Keywords
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