Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

Abstract

Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints. The authors analyze the algorithms and comment on their implementation. They report experimental results, including the design and testing of a 63-bit population counter in CML bipolar technology. A brief analysis of circuit technologies shows that CML and super-buffered ECL without stacked structures are well suited for wave pipelining because they have uniform delay. Static CMOS and ordinary ECL including stacked structures and emitter-followers do have some delay variations. A high degree of wave pipelining is still possible in those technologies if special design techniques are followed