A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies
- 1 December 2014
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 729 (01631918), 32.3.1-32.3.4
- https://doi.org/10.1109/iedm.2014.7047154
Abstract
A new scheme called in the following “Diffusion and Gate Replacement” (D&GR) MIPS integration is demonstrated. The CMOS flow allows to control the gate height asymmetry between NMOS and PMOS by driving the work function shifter directly into the high-k. Since the threshold voltage (Vth) shifter sources are removed, it is compatible with other processes requiring high-thermal budget such as memory technologies (DRAM periphery).Keywords
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