Hierarchy Optimization: A Means to Enhance Efficiency in E-Beam and Optical Lithography

Abstract

In the e-beam lithography arena the proximity effect correction (PEC) of large la youts is still regarded as an insurmountable hurdle. The central processing unit (CPU) time for today's memory layouts (64 Mb) extends into weeks and file sizes into Gigabytes. In this paper a new concept for hierarchical data handling is introduced, the hierarchy reorganization. It paves the way for practical applications of very large layouts. The initial layout is reorganized according to correction-dependent criteria. The term hierarchy factor, which is a measure of the compaction of the given hierarchy tree, is introduced. This paper presents and explains the theoretical rules of the hierarchy optimization. The problems of hierarchical processing are demonstrated and solutions given. The solutions fall into two categories: the first one is common to all hierarchical processing, whereas the second one is application-specific. As an example, the hierarchical processing is applied to the proximity effect correction. Scanning electron microscope (SEM) images of memory chips are shown by comparing corrected with uncorrected wafers. Files sizes and processing times of all relevant processing steps in comparison with flat operation (not exploiting the hierarchy) are given.