Differential split-level CMOS logic for sub-nanoseconds speeds
- 1 January 1985
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Surface conduction in short-channel MOS devices as a limitation to VLSI scalingIEEE Transactions on Electron Devices, 1982
- Hot-electron injection into the oxide in n-channel MOS devicesIEEE Transactions on Electron Devices, 1981
- Design and performance of micron-size devicesSolid-State Electronics, 1978