FFT processor using field programmable gate arrays

Abstract

The design and construction of a hardware fast Fourier transform processor are presented. The hardware relies principally on field programmable gate arrays (FPGAs). The hardware architecture is based on Tukey-Cooley butterfly algorithms. It uses 218 configurable logic blocks (CLBs) and 42 input-output processors (IOBs) and implements a simple parallel processing architecture. The input of the processor is 16 real-value points and the output is complex. The execution time of the transform is estimated to be 0.736 ms.