Holding time distribution in dynamic MOS RAMs

Abstract

By continuously increasing the period between alternate write and read cycles it is possible to represent the topographic and temporal distribution of failing memory cells of DRAMs. Recording, for example, the first fail bit of each die on a wafer at 85^° C, the resulting holding time histogram exhibits a characteristic profile. A failure maximum at low holding times (t_H ≲ 40 ms for the 64 K DRAM) is followed by a minimum and then by a second, much more pronounced maximum. Failures up to the leading edge of the second maximum are determined by generation-dependent leakage currents (activation energy E_A ≈ 0.55 eV). The position of the second maximum is characteristic of the substrate material and the temperature profile of the overall process. The failure mechanism is determined by diffusion and the temperature dependence of the leakage current is characterized by an activation energy of E_A ≈ 1.1 eV. In the 64 K DRAM produced on float-zone silicon, the diffusion current maximum lies between 800–1000 ms at 85^° C in a suitably designed device (e.g. potential sinks at the cell field edge). For DRAM devices produced on crucible-drawn silicon, the diffusion-dependent leakage rate increases super-proportionally with the oxygen content. The diffusion current maximum can therefore drop to about 50 ms when the initial oxygen content is high.