Fault Equivalence in Combinational Logic Networks

Abstract

This paper is a study of the effects of faults on the logical operation of combinational (acyclic) logic circuits. In particular, the conditions whereby two different faults can produce the same alteration in the circuit behavior are investigated. This relationship between two faults is shown to be an equivalence relation, and three different types of equivalence relations are specified. Necessary and sufficient conditions for the existence of these equivalence relations are proved. An algorithm for determining the equivalence classes for one of the types of equivalence is presented. Other types of algebraic properties of faults are discussed.