Supercomputing with spin-polarized single electrons in a quantum coupled architecture

Abstract

We describe a novel quantum technology for possible ultra-fast, ultra-dense and ultra-low-power supercomputing. The technology utilizes single electrons as binary logic devices in which the spin of the electron encodes the bit information. Both two-dimensional cellular automata and random wired logic can be realized by laying out on a wafer specific geometric patterns of quantum dots each hosting a single electron. Various types of logic gates, combinational circuits for arithmetic logic units, and sequential circuits for memory have been designed. The technology has many advantages such as (1) the absence of physical interconnects between devices (inter-device interaction is provided by quantum mechanical spin-spin coupling between single electrons in adjacent quantum dots), (2) ultra-fast switching times of approximately 1 picosecond for individual devices, (3) extremely high bit density approaching 10 terabits cm^-2, (4) non-volatile memory, (5) robustness and possible room-temperature operation with very high noise margin and reliability, (6) a very low power delay product ( approximately 10^-20 J) for switching between logic levels, and (7) a very small power dissipation of a few tens of nanowatts per switching event. In spite of the above advantages, the technology also has some serious drawbacks in that the fan-out of individual logic devices may be small, wiring crossover is very problematic and the devices themselves have no inherent gain so that isolation between input and output is virtually non-existent. These are problems that plague all similar quantum technologies although they are seldom recognized as such. We will discuss these problems, and where possible, offer plausible solutions. In spite of these drawbacks, however, there are still enough attractive features of this technology to merit serious research. In this paper, we will describe how the spin-polarized single-electron logic devices work, along with the associated circuits and architecture. Finally, we will propose a new fabrication technique for realizing these chips which we believe is much more compatible with the demands of the technology than conventional nanofabrication methods.