Parallelization of WHILE loops on pipelined architectures
- 1 October 1991
- journal article
- Published by Springer Nature in The Journal of Supercomputing
- Vol. 5 (2), 119-136
- https://doi.org/10.1007/bf00127840
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- The Cydra 5 computer system architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offsComputer, 1989
- Conversion of control dependence to data dependencePublished by Association for Computing Machinery (ACM) ,1983
- A composite hoisting-strength reduction transformation for global program optimization part IInternational Journal of Computer Mathematics, 1982
- Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computingACM SIGMICRO Newsletter, 1981
- An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 FamilyComputer, 1981