High-performance bit-serial adders and multipliers

Abstract

A design methodology is presented which uses clocked logic modules to synthesise flexible high performance multipliers. By using two-stage pipelined bit-serial adders, a bit-serial multiplier can be designed which is capable of producing both single- and double-precision products for continuous two's complement data streams. High processing speeds are possible owing to the systolic structure which is pipelined at the gate level.