The application of test structures for the study of surface effects in LSI circuitry

Abstract

The successful development of LSI circuitry with multilevel metallization requires the development of practical means for insuring the highest level of performance and reliability. This requires the development of a broad fundamental understanding of the factors that affect the semiconductor-insulator interface and of practical means for measuring the fundamental properties of this Interface. A comprehensive model has been developed that includes each of the known factors that influences the electrical properties of the semiconductor-insulator interface. The design and use of test structures for measuring the effects of each of these factors are discussed. Test structures are shown to be useful for the preliminary evaluation, development, and control of materials, techniques, equipment, and processes, and for reliability assessment. The test structures are useful in connection with both MOS and bipolar circuits and over the entire range of circuit complexity. Effects of variations in materials or processes on the electrical properties of the interface are given. Experimental data are given that demonstrate the utility of test structures for the evaluation of materials, process, and structural designs, and for production controls and reliability assessment.