A monolithic 16 x 16 digital multiplier
- 1 January 1974
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The design, fabrication and testing of a 16 × 16 multiplier chip, will be described. The circuit contains 17,000 transistors and resistors on a 301 × 279-mil chip and does a multiplication in less than 350 ns.Keywords
This publication has 1 reference indexed in Scilit:
- A large-scale integrated correlatorIEEE Journal of Solid-State Circuits, 1972